Automatic Asset Identification in RTL
Python toolkit to detect potential primary assets in Verilog/SystemVerilog using keyword and behavioral rules; supports CSV export and hierarchy traversal.
👋 Hello! I’m Subroto
Embedded/Firmware Engineer &
Embedded/Firmware Engineer &
Digital Hardware Engineer
MSc in Electrical Engineering at the University of Calgary focused on automatic asset identification in RTL, and an R&D engineer with 4+ years of experience delivering digital products, embedded systems, and firmware across STM32, AVR, PIC, RISC-V, ESP32, and more.
Skills
C / Embedded C
Python
Verilog / SystemVerilog
ARM Cortex-M
RISC-V
STM32
AVR
PIC (PIC24F16KA101)
ESP32
Digital Design (FPGA/ASIC)
Hardware Security
Signal Flow Analysis
Git / GitHub
CI/CD Basics
Highlighted Projects
Signal Flow Graph for OpenTitan
Scripts to trace inter-module connections (incl. hw2reg/reg2hw) from top to leaf for assets like keymgr_key_i.
CTMU-Based Capacitance Meter
Custom meter built on PIC24F16KA101 using CTMU to measure capacitance with improved accuracy over low-cost multimeters.
Experience & Education
Graduate Researcher — Univ. of Calgary
2023–2025 · Calgary, Canada
Thesis: Automatic Asset Identification in RTL Code; developed automated tools for CIA tagging, hierarchical tracing, and evaluation on open-source IPs.
R&D Engineer — Walton Digi-Tech Industries
2018–2021 · Dhaka, Bangladesh & Shenzhen, China
Led cross-functional teams delivering digital consumer products (laptops, tablets, EVM monitor). Firmware development, BIOS tooling, production optimization.
B.Sc. in EEE — (Your University)
Year–Year · City, Country
Focus: Embedded systems, digital design, signal processing.
Publications & Awards
Certifications
Contact
Open to roles in embedded systems, firmware, digital hardware/RTL, and hardware security. For collaborations or opportunities, reach out!
Get in touch
Email: subroto.ece.ku@gmail.com
GitHub: subrotoece
LinkedIn: Subroto Nath